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The 16th IEEE International Workshop on
Memory Technology, Design, and Testing (MTDT 2009)

August 31 - September 2, 2009

Ambassador Hotel, Hsinchu
Hsinchu, Taiwan

http://nthucad.cs.nthu.edu.tw/~mtdt09/

Submission Deadline Extended to May 3rd, 2009!
CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

Following the traditions set up by its predecessors, MTDT09 will provide a forum dedicated to the recent advancements of the memory technology, covering topics such as memory device, circuit design, architecture, fabrication process, verification, yield analysis testing/diagnosis/repair for all kinds of memory such as SRAM, DRAM, Flash memory, EPROM, EEPROM, embedded memories, 3-D memories, content addressable memories, etc.

Original contributions related to memory design and test technology are solicited. Topics of interest include, but are not limited to, the following categories:

  • Next-generation memory device
  • Next-generation memory process
  • Low-voltage memory circuit design
  • 3D memories
  • Volatile memory devices
  • Non-volatile memory devices
  • High-speed memory circuit design
  • Low-power memory circuit design
  • Fault-tolerant architecture
  • Memory compiler
  • Memory testing
  • Memory built-in self-test
  • Memory diagnosis & repair
  • Cell Characterization
  • Failure analysis
  • Fault modeling
  • Yield analysis
  • Reliability analysis
  • Memory for space application
  • Verification methodology
  • Design and test for SSD

Submissions

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Web page: http://nthucad.cs.nthu.edu.tw/~mtdt09/
Submission deadline: extended to May 3rd, 2009

If you encounter problem in submitting the paper via web page, please send your manuscript and information to the Program Chair, Chih-Tsun Huang, via email cthuang@cs.nthu.edu.tw.

Key Dates

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Submission deadline: extended to May 3, 2009
Notification of acceptance:May 22, 2009
Final copy deadline: June 8, 2009

Committees
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ORGANIZING COMMITTEE

General Co-Chairs
Cheng-Wen Wu, National Tsing Hua U., Taiwan
Rochit Rajsuman, San Jose State-U, USA

Program Chair
Chih-Tsun Huang, National Tsing Hua U., Taiwan

Finance Chair
Meng-Fan Chang, National Tsing Hua U., Taiwan

Local Arrangements Chair
Jen-Chieh Yeh, SOC Technology Center, ITRI, Taiwan

Publications Chair
Jin-Fu Li, National Central U., Taiwan

Registration Chair
Shyue-Kung Lu, Fu-Len Catholic U., Taiwan

PROGRAM COMMITTEE

For the list of the Program Committee members see http://nthucad.cs.nthu.edu.tw/~mtdt09/

For more information, visit us on the web at: http://nthucad.cs.nthu.edu.tw/~mtdt09/

The IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2009) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel.
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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